CD-ROM Now 11/CD-ROM Now MegaDisc 11 (1995-02).iso/discs/internet/lsi3.txt

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From: [e-mail] (Michael Altarriba)
Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 3/4) [LONG]
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Archive-name: lsi-cad-faq/part3

  (From comp.dsp FAQ)

  Ptolemy provides a highly flexible foundation for the specification,
  simulation, and rapid prototyping of systems.  It is an object oriented
  framework within which diverse models of computation can co-exist and
  interact.  For example, using Ptolemy a data-flow system can be easily
  connected to a hardware simulator which in turn may be connected to a
  discrete-event system, etc.  Because of this, Ptolemy can be used to
  model entire systems.

  In addition, Ptolemy now has code generation capabilities.  From a flow
  graph description, Ptolemy can generate both C code and DSP assembly code
  for rapid prototyping.  Note that code generation is not yet complete,
  and is included in the current release for demonstration purposes only.

  Ptolemy has been used for a broad range of applications including signal
  processing, telecomunications, parallel processing, wireless communica-
  tions, optical phase lock loops, real time systems, and hardware/software
  co-design.  Ptolemy has also been used as a lab for signal processing and
  communications courses.  Currently Ptolemy has hundreds of users in over
  75 sites, both in industry and academia.

  Ptolemy is available for the Sun 4 (sparc) and DecStation (MIPS) archi-
  tectures.  A port to the HP workstation is in progress.  Installing the
  system requires 49 Mbytes for Ptolemy (64 Mbytes after you optionally
  rebuild) and 16 Mbytes for the Gnu tools subset.  At least 8 Mbytes of
  physical memory are required.

  Ptolemy has been developed at UC Berkeley over the past 3 years.  Further
  information, including papers and the complete release notes, is avail-
  able from the FTP site.

  A license is no longer required to receive Ptolemy.  The source code,
  binaries, and documentation are available by anonymous ftp from
  ptolemy.berkeley.edu, under /pub/ptolemy. Consult the file /pub/README
  for further information.

24: Lager (Current version 4.0):

  (From MUG 18)

  The LAGER system is a set of CAD tools for performing parameterized VLSI
  design with a slant towards DSP applications (but not limited to DSP
  applications).  A standard cell library, datapath library, several module
  generators and several pad libraries comprise the cell library.  These
  tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
  sippi State, and ITD.  The tool development has been funded by DARPA
  under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
  ley).  LAGER 3.0 was described in MUG 15.

  Send email to [e-mail] if you are interested in obtaining
  the toolset via FTP. If you cannot get the distribution via ftp then send
  one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
  by phone at (601)-325-3670 or at one of the following addresses:

          (US Mail Address)
          P.O. Box 6176
          Mississippi State, MS 39762

          (FEDEX)
          2 Research Boulevard
          Starkville, MS 39759

  Be sure to include a return FEDEX waybill we can use to ship your tape
  back to you. Instead of sending a tape and FEDX waybill, you can also
  just send us a check for $75 and we will send you back a tape.  Make the
  check payable to Mississippi State Univ.  The tape will be written on a
  high density tape drive (150 Mb).  Older low density SUN tape drives (60
  Mb) cannot read this format so you need to have access to one of SUN's
  newer tape drives.

25: BLIS (Current version 2.0):

  (From their announcement posted here)

  BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
  synthesis of digital circuits from high-level descriptions.  Version 2.0
  supports functional-level synthesis starting from the ELLA hardware
  description language.  Other languages can easily be supported by inter-
  facing a parser to the internal data-flow representation of BLIS.

  BLIS is distributed through the Industrial Liason's Program (ILP) Office
  of the UCB EECS department.  The cost of $250 covers media and distribu-
  tion charges.  Binaries are provided for SUN4 and DEC MIPS architectures
  but BLIS should compile on most other machines supported by the GNU C and
  C++ compilers (e.g. HP, vax, etc).  ELLA language documentation and simu-
  lator are not supplied with the BLIS distribution, but can be obtained
  from Computer General.

26: COSMOS and BDD

  (From their announcement posted here)

                Obtaining and installing COSMOS and BDD.

  The COSMOS package generates switch-level simulators for MOS circuits.
  The BDD package is a subset of COSMOS providing a set of library routines
  for symbolic Boolean manipulation.

  To obtain a copy of either COSMOS or BDD via FTP:

  1. Create an appropriate subdirectory.  For COSMOS, you may want to
     create a symbolic link /usr/cosmos to this directory, although this is
     not essential.

  2. Connect to the subdirectory

  3. FTP to n3.sp.cs.cmu.edu (login anonymous, password
     [e-mail])

  4. Type:

             cd /usr/cosmos/ftp
             ls

  5. Select which version of the code you want.  The files are named
     bdd.XXX.YYY.tar.Z and cosmos.XXX.YYY.tar.Z, where XXX.YYY is the ver-
     sion number.  Generally you should select the highest numbered ver-
     sion.

  6. 6. Type:
             get <FILE> (where <FILE> is the file name of the selected ver-
     sion).
             get README
             quit

  7. Follow the instructions in README

  8. Send the following information to [e-mail]

             Your name
             Your postal address
             Your net address
             The file retrieved
             The date of your retrieval

  COSMOS and BDD are made available with the understanding that no part of
  it will be redistributed further without permission.

  Last updated 18 July 1991 by Derek Beatty.

  27: ITEM

  (Taken from the item.news file contained in the package:)

  The first public release of ITEM, UCSC's logic minimizer using if-then-
  else DAGs, was made 2 January 1991.  The system is available by anonymous
  ftp from ftp.cse.ucsc.edu, in directory pub/item as a compressed tar
  archive (item.tar.Z).  Also available are tech reports about the algo-
  rithms and data structures (88-28, 88-29, and 90-43).

  ITEM can also be found at ftp.cse.ucsc.edu in the pub/item directory.

28: PADS logic/PADS PCB:

  While this is a commercial product, they have just recently made avail-
  able a shareware version.  This version is fully functional and indenti-
  cal to their schematic capture and PCB autoplace and route software
  except that it is limited to about 50 components.  It is available for
  IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at
  several sites including wuarchive.wustl.edu in
  /mirrors/msdos/cad/pads*.zip.  There is a $50 registration fee if you
  would like to get future updates from them.

29: Another PCB Layout Package:

  (from Randy Nevin <[e-mail]>:)

  I'm distributing a freely-copyable software package to do autorouting of
  (1- and 2-layer) printed circuit boards on a PC or compatible. It is
  written in C (with a little .asm), and all source code is included. There
  is an autorouter, a board viewer, a rat nest viewer, and some output
  filters which generate postscript and hp laserjet output files. There is
  no charge, but I maintain the copyright (it is not public domain). If you
  want to read about it, I published an article on autorouting algorithms
  in the sept '89 dr. dobb's journal. ega is required (for the viewing pro-
  grams). If you'd like to get the software, send me a stamped, self-
  addressed floppy mailer and a floppy. I can handle 5.25" 360K or 1.2M, or
  3.5" 1.4M, but if you send 360K there is some extra code that I won't be
  able to fit on the disk, so high density is better.

  I developed this software at home on my own time, and it is not related
  to what I do for my employer, so I will not use my employer's email
  resource to distribute it. however, it is available for anonymous ftp
  access on wsmr-simtel20.army.mil in PD1:<MSDOS.CAD>PCB.ARC, last I heard.
  I do not keep simtel up to date. But the version there is useable, and
  does include all source code.

          Randy Nevin
          24135 SE 16th PL
          Issaquah, WA 98027

30: Magic (Current version 6.3):

  This is a polygon based lsi layout editor.  It is capable of reading and
  writing magic, calma (version 3.0, corresponding to GDS II Release 5.1),
  and cif.  It is available for anonymous ftp from gatekeeper.dec.com in
  /pub/DEC/magic.

31: PSpice:

  This is a commercial product, however, they do have a student version
  that is available (limited to around 16 transistors).

          PC dos version: 5.0 wuarchive.wustl.edu in
                          /mirrors/msdos/electrical/,
                          pspice5a.zip, pspice5b.zip, pspice5c.zip

          PC windows3 version 5.1: WSMR-SIMTEL20.Army.Mil in
                          pd1:<msdos.windows3>
                          called PSPIC51A.ZIP and PSPIC51B.ZIP

          Mac version 5.1: wuarchive.wustl.edu in
                          /mirrors/info-mac/app/pspice-51.hqx

  The PC version is also available at a number of U.S. and non-U.S. sites.

32: Esim:

  A new version of the switch-level simulator ESIM that can handle CMOS
  transmission gates is available through MUG, ftp venera.isi.edu
  (128.9.0.32))

33: Isplice3 (Current version 2.0):

  This is a high level simulator, I do not know much more then that.  It is
  available via anonymous ftp from uicadb.csl.uiuc.edu.

34: Watand:

  (From Phil Munro <[e-mail]>)

    This posting will give the interested person some information about the
  WATAND (WATerloo ANalysis and Design) circuit simulator.  Watand was
  introduced at the 16th Midwest Symposium on Circuit Theory (1973).  In
  spite of its lack of advertising, Watand still offers some advantages
  when compared with other well known circuit simulators.  For example it
  is a *truly* interactive simulator; that is, one enters the "WATAND"
  environment in which analyses and design can be run and rerun, values
  changed, settings queried and changed, etc.

    Watand uses piecewise-linear as its primary simulation; other methods
  are optional.  It has ten built-in analyses which include the standard
  dc, ac, and transient analyses, and two post-processors (display and
  discrete Fourier).  Output may be in the form of printed tables; graphics
  display includes Tektronix 40xx output.  At YSU interactive helps are
  also available.

    Watand provides for the creation and use of user defined elements in
  addition to its own good stock of 34 built-in elements plus 21 built-in
  user defined elements.  User defined analyses and post-processors can
  also be written, and it includes a powerful macro facility.

    As of June, 1992, sale of the Watand simulator was still being handled
  by Mark O'Leavey, Waterloo Engineering Software, 22 King St. S., Suite
  302, Waterloo, Ontario, CANADA, N2L 1C6, Fax: [phone]; Phone:
  [phone].  At that time I was informed that it was available only
  for DECStation and Sparcstation, although we are running it quite suc-
  cessfully at YSU under the CMS operation system on an Amdahl mainframe.

    Two new and helpful manuals are available for the simulator.  They
  should be available at the Youngstown State University Bookstore, Youngs-
  town, OHio 44555:  Their approximate cost should be $7 each:

          "WATAND Users Manual," by Dr. Phil Munro, Youngstown State
          University, April 1992, 233 pages, 10 chapters, 4 appendices,
          index.

          "WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown
          State Unversity, June 1992, 204 pages, 12 chapters, index.

    Watand does *not* include digital simulation at this time, nor does it
  have any transmission-line elements.  A self-heating BJT model has been
  developed and is proving useful.  Monte Carlo statistical simulation is
  possible with dc and ac analyses using macro based analyses which have
  been developed at YSU.

35: Caltech VLSI CAD Tools:

  (From John Lazzaro <[e-mail]>)

                     Caltech VLSI CAD Tool Distribution

  We are offering to the Internet community a new revision of the Caltech
  electronic CAD system for analog VLSI neural networks.  This distribution
  contains tools for schematic capture, netlist creation, and analog and
  digital simulation (log), IC mask layout, extraction, and DRC (wol), sim-
  ple chip compilation (wolcomp), MOSIS fabrication request generation
  (mosis), netlist comparison (netcmp), data plotting (view) and postscript
  graphics editing (until). These tools were used exclusively for the
  design and test of all the integrated circuits described in Carver Mead's
  book "Analog VLSI and Neural Systems".  Until was used as the primary
  tool for figure creation for the book.  The distribution also contains an
  example of an analog VLSI chip that was designed and fabricated with
  these tools, and an example of an Actel field-programmable gate array
  design that was simulated and converted to Actel format with these tools.

  These tools are distributed under a license very similar to the GNU
  license; the minor changes protect Caltech from liability.

  Highlights of the new revision includes:

          * Ports to new platforms (Supported platforms now include: Sun SPARC,
            Sun 3, HP Series 300/400/700/800, DEC MIPS-based Ultrix, Apple AU/X,
            linux, and IBM RS/6000 support).

          * Support for black and white displays, and resource database support
            for user preferences for sizing and placement of windows. New
            display modes in analog to support small screens.

          * Direct generation of SPICE netlists in analog, and new models
            for floating-well FET's, two-terminal devices with arbitrary i-v
            curves, and quantum-well tunnel diodes.

          * Many bug fixes for analog, wol, view, and until, and new features
            for view.

          If you are interested in some or all of these tools,

          1) ftp to hobiecat.pcmp.caltech.edu on the Internet,
          2) log in as anonymous and use your username as the password
          3) cd pub/chipmunk
          4) copy the file README, that contains more information.

  European researchers can access these files through anonymous ftp using
  the machine ifi.uio.no in Norway; the files are in the directory chip-
  munk.  We are unable to help users who do not have Internet ftp access.

  A small but rather important bug was found in the "analog" program of the
  new Chipmunk distribution announced several weeks ago -- a key MOS
  transistor parameter was off by an order of magnitude! The current copies
  of the distribution on hobiecat.caltech.edu and ifi.uio.no have this bug
  corrected; however, if you've already picked up and installed the distri-
  bution since the new release (early april), here are the directions for
  patching your current installation w/o bringing over and rebuilding the
  whole package:

          1) anonymous ftp to hobiecat.pcmp.caltech.edu, cd to pub/chipmunk
          2) get the file models.cnf
          3) in your distribution, use this file to replace log/lib/models.cnf

    That's it! Sorry for the inconvenience ...

36: Switcap2 (Current version 1.1):

  This is a switched capactor simulator.  It is available from:

                  SWITCAP Distribution centre,
                  411 Low Memorial Library,
                  New York,
                  N.Y. 10027.

37: Test Software based on Abramovici Text:

  (Contributed by Mel Breuer of the Univ. of Southern California)

  Many faculty are using the text by Abramovici, Breuer, and Fried- man
  entitled  "Digital Systems Testing and Testable Design" in a class on
  testing.  They have expressed an interest to  supplement their  course
  with software tools.  At USC we have developed such a suite of tools.
  They include a  good  value  simulator,  fault simulator,  fault  col-
  lapsing  module, and D-algorithm-based ATPG module for combinational
  logic.  The software has  been  specifi- cally  designed  to  be easily
  understood, modified and enhanced.  The algorithms follow those described
  in the text.  The  software can  be  run  in many modes, such as one
  module at a time, single step, interactively or as a batch process.  Stu-
  dents can use  the software  "as  is"  to  study  the operation of the
  various algo- rithms, e.g. simulation of a latch using different delay
  models.  Also,  simple  programming  projects can be given, such as
  extend the simulator from a 3-valued system to  a  5-valued  system;  or
  change  the D-algorithm so that it only does single path sensiti- zation.
  There  are  literally  over  50  interesting   software enhancements
  that  can  be made by changing only a small part of the code.  The system
  is written in C and runs on a SUN.

  If you are currently using the Abramovici text and would  like  a copy
  of  this  software,  please  send a message to Prof. Melvin Breuer at
  [e-mail].

38: Test Generation and Fault Simulation Software

  (Contributed by Dr. Dong Ha of Virginia Tech)

  Two automatic test pattern generators (ATPGs) and a fault simula- tor
  for  combinational circuits were developed at Virginia Tech, and the
  source codes of  the  tools  are  now  ready  for  public release.
  ATLANTA is an ATPG for stuck-at faults.  It is based on the FAN algorithm
  and a parallel-pattern,  single-fault  propaga- tion  technique.   It
  consists of optional sessions using random pattern testing, deterministic
  test pattern generation  and  test compaction.  SOPRANO is an ATPG for
  stuck-open faults.  The algo- rithm of SOPRANO is similar to  ATLANTA
  except  two  consecutive patterns  are  applied  to  detect a stuck-open
  fault.  FSIM is a parallel-pattern, single-fault  simulator.   All  the
  tools  are written  in  C.  The source codes are fully commented, and
  README files contain user's manuals.  Technical papers about  the  tools
  were  presented at DAC-90 and ITC-91. All three tools are free to univer-
  sities.  Companies are requested to make a contribution  of $5000  but
  will have free technical assistance.  For detailed in- formation, con-
  tact:

             Dr. Dong Ha
             Electrical Engineering
             Virginia Tech
             Blacksburg, VA 24061
             TEL: [phone]
             FAX: [phone]
             [e-mail]

39: Olympus Synthesis System

  (From Rajesh K. Gupta <[e-mail]>)

  Recently there have been several enquiries about the Olympus Synthesis
  System. Here are answers to some commonly asked questions. For details
  please send mail to "[e-mail]".

  1. What is Olympus Synthesis System?

  Olympus is a result of a continuing project on synthesis of digital cir-
  cuits here at Stanford University. Currently, Olympus synthesis system
  consists of a set of programs that perform synthesis tasks for synchro-
  nous, non-pipelined circuits starting from a description in a hardware
  description language, HardwareC.

  The output of synthesis is a technology independent netlist of gates.
  This netlist can be input to logic synthesis and technology mapping tools
  within Olympus or to UC Berkeley's mis/sis. Current technology mapping in
  Olympus is targeted for LSI logic standard cells and a set of PGA archi-
  tectures: Actel and Xilinx.

  2. How is Olympus distributed?

  The source code and documentation for Olympus is distributed via ftp.

  3. What are the system requirements for Olympus?

  Olympus has been tested on following hardware platforms: mips, sparc,
  hp9000s300, hp9000s800, hp9000s700, vax.  All the programs in Olympus
  come with a default menu-driven ASCII interface. There is also a graphi-
  cal user interface, called "olympus", provided with the distribution.
  This interface is written using Motif procedures.

  You would need about 40 MBytes of disk space to extract and compile the
  system.

  4. How can I obtain a copy of Olympus?

  Olympus is distributed free of charge by Stanford University.  However,
  it is not available via anonymous ftp. In order to obtain a copy please
  send a mail to "[e-mail]" where an automatic-reply
  mailer would send instructions for obtaining Olympus software.

40: OASIS logic synthesis

  (From William R. Richards Jr. <[e-mail]>)

  OASIS is a complete logic synthesis system based on the Logic3 HDL
  develped at MCNC (unfortunately neither VHDL or Verilog compatible).
  [e-mail] is the person responsible for it. OASIS is available to US
  universities for $500 and non-US universities for $600. Industrial
  license is $3000.

41: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator

  (From William R. Richards Jr. <[e-mail]>)

  CAzM is a Spice-like table-based analog circuit simulator. It offers sig-
  nificant performance advantages over other Berkeley Spice derivatives. It
  is used fairly extensively in our design community.  US university
  license is $175, non-US $250. Commercial license is $800. It comes with
  an X11- based signal viewing tool Sigview which is public domain and may
  be anonymous ftp'd from mcnc.org. I am the primary contact for CAzM at
  MCNC.

  (From Bhusan Gupta <[e-mail]>)

  The CAzM program that was developed and offered by MCNC, has been
  licensed for distribution by Tanner Research, Inc. of Pasadena, CA and
  all future product availability and support is available from Tanner
  Research.  The program as offered by Tanner Research is a commercial pro-
  duct and is now named T-Spice.  This Spice-like simulator offers table-
  based model evaluations for fast simulation performance, as well as,
  included analytical models for use with digital and analog circuits.
  Improvements to the CAzM models have also been made.  Tanner Research
  offers an optional Advance Model Library of charged controlled models
  that includes an accurate, physically-based MOSFET model that is continu-
  ous over all transistor regions of operations (including subthreshold),
  and scales to submicron channel lengths.  User defined models of any cus-
  tom component or circuit written in "C" can be readily linked to T-Spice
  as a general n-terminal device.  Pricing is $995 for the simulator and
  $1,245 with the Advance Model Library and Waveform Viewer.  Universities
  are offered a 75% discount.  A modeling and extraction service is  also
  provided by Tanner Research to generate functional or transistor level
  circuit simulation models for user supplied devices.  The extraction ser-
  vice provides extracted model parameters for existing circuit simulation
  models, such as SPICE models, Tanner's own charge controlled MOS models,
  or user's proprietary models.  In addition, software is available to aid
  users in extracting model parameters in house.  For more information con-
  tact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone
  818-792-3000 and fax [phone].

42: Galaxy CAD, integrated environment for digital design for Macintosh

  Thanks to Simon Leung <[e-mail]>

  The Galaxy CAD System is an integrated environment for digital design and
  for rapid prototyping of CAD tools and other software.  The system
  currently includes schematic capture and simulation of both low-level and
  high-level digital designs and is being expanded to include physical
  design tools.  Galaxy runs on a number of 680X0 platforms, including the
  Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST.  Others will be
  added according to demand.

  The Galaxy CAD System is an ideal environment for teaching digital
  design.  It has been used successfully for both introductory logic design
  and computer design courses at Wisconsin.  Some of the features of Galaxy
  that make it suitable for education are:

  1.  Integrated multiple-window environment: All Galaxy tools run
      concurrently in a multiple window environment.  Copying data
      from one window to another is simple.  Any number of simulation
      sessions can be active simultaneously.

  2.  Hierarchy: the schematic editor and simulator are both fully
      hierarchical.  Building hierarchical designs is simple, including
      creating symbols for modules.  The simulator is a true hierarchical
      simulator: it does not require a time-consuming macro-expansion
      step.

  3.  Integrated editing and simulation: Designs are edited and
      simulated in the same environment.  Simulation input and output
      can be shown directly on schematics, allowing direct manipulation
      of net values.  Unlike other products, Galaxy does not require
      modification of the schematic to insert "switch" and "light"
      components.  In addition, Galaxy allows display of bus values in
      hexadecimal directly on schematics to simplify debugging of
      high-level designs.  Simulation I/O can also use waveforms,
      text files, and tables.

  4.  Faults: Stuck-at faults can be introduced on the schematic
      editor and simulated immediately without rebuilding the
      simulation model.  This provides an excellent way to display
      the effects of faults.

  5.  Buses: Galaxy supports specification and simulation of bus
      structures, including complex extractions, fanouts, and bit
      reversal.  Buses are specified by annotating nets with text.
      For simulation, buses are kept intact so that multiple-bit
      high-level components can be used.  Galaxy includes a library
      of register-transfer components suitable for high-level
      computer design and simulation.

  6.  Alternate specification of designs: In addition to schematics,
      Galaxy users can specify design modules using a textual HDL
      (GHDL) and using hardware flowcharts and state diagrams.  A
      hierarchical design can mix these representations as desired.

  7.  High-quality PostScript output: Galaxy schematics are of excellent
      quality.  Gates are drawn according to standard practices, e.g.,
      OR gates are drawn with the correct circular arcs and not ellipses.

  8.  Uniform user interface: Galaxy tools have the same user interface
      on all platforms, reducing student learning curves.  In fact,
      the same tool OBJECT CODE runs on all platforms due to the unique
      structure of Galaxy.

  9.  Adding new simulation primitives is straightforward.

  10. No cost: Galaxy is available for free via anonymous FTP (Apple
      Macintosh version).  Other versions will be made available based
      on demand.

  Galaxy is also an excellent environment for rapid prototyping of new CAD
  tools.  By building on top of available resources, we have been able to
  prototype new tools in days or weeks that would ordinarily have taken
  months or years.  For more information, send e-mail.

  To obtain Galaxy CAD, connect to "eceserv0.ece.wisc.edu" using FTP.  Log
  in as "anonymous" with password "guest".  Galaxy is in directory
  "pub/galaxy".  The file "README" in that directory gives further instruc-
  tions.  Please register as a user by sending e-mail to
  "[e-mail]".

  John F. Beetem
  ECE Department
  University of Wisconsin - Madison
  Madison, WI  53706
  USA
  [phone]
  [e-mail]

43: Gabriel DSP development system

  The Gabriel software is available via ftp from copernicus.Berkeley.EDU
  (128.32.240.37).  It's not quite "anonymous": you can use anonymous ftp
  to get the license agreement.  When you sign that and mail it back to us,
  we give you the password to an ftp account that allows you to grab the
  actual software.  It's free, just not anonymous.  :-)

  For the uninitiated, Gabriel is a block diagram programming environment
  for DSP that runs on Sun 3 and Sun 4 workstations.  It can simulate DSP
  designs, generate assembly code for Motorola DSP56000 and DSP96000 chips,
  and automatically perform parallel scheduling when multiple DSP chips are
  used.

  For more information, ftp to copernicus.Berkeley.EDU, log in as
  "anonymous" (any password will do), and grab the files "gabriel-
  overview", "gabriel-release-info", and "gabriel-license.shar".  Be warned
  that a new version of Gabriel will be out by the end of January, so if
  you're interested in it, it might pay to wait until then.

  Phil Lapsley
  [e-mail]

44: WireC graphical/procedural system for schematic information

  (From Larry McMurchie <[e-mail]>)

  WireC is a graphical specification language that combines schematics with
  procedural constructs for describing complex microelectronic systems.
  WireC allows the designer to choose the appropriate representation,
  either graphical or procedural, at a fine-grain level depending on the
  characteristics of the circuit being designed.  Drawing traditional
  schematic symbols and their interconnections provides fast intuitive
  interaction with a circuit design while procedural constructs give the
  power and flexibility to describe circuit structures algorithmically and
  allow single descriptions to represent whole families of devices.

  The procedural capability of WireC allows other CAD tools to be incor-
  porated into the design system.  For example, we have defined an inter-
  face to the SIS logic synthesis system wherein the designer can represent
  part of the system behaviorally.  WireC invokes logic synthesis on these
  components to produce a structural description that can be incorporated
  into the rest of the design.

  Libraries of devices defining a particular netlist output format may be
  defined by the user. The libraries currently distributed with WireC
  include a default CMOS gate library whose output is the SIM format.  This
  format can be simulated with COSMOS or IRSIM and compared against a cir-
  cuit extracted from layout.  This library also includes devices that
  allow a behavioral description to be synthesized and mapped using MIS or
  SIS and incorporated into a larger circuit.

  Another library is the xnf library for designing systems with Xilinx
  FPGAs.  Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC,
  this library contains devices specific to the 2000 and 3000 series Xilinx
  LCA's.  In addition to drawing the devices explicitly, one can represent
  parts of a circuit with equations and have these synthesized automati-
  cally.

  Currently in progress is a library of CMOS gates for Cascade Design
  Automation's ChipCrafter product.  WireC provides a mixed
  schematic/procedural design frontend for ChipCrafter, which uses module
  generation, timing analysis and place and route software to create a phy-
  sical layout from the WireC design specification.

  WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed
  Tellman.  We are interested in any libraries you may develop and will
  provide a limited degree of support.

  WireC requires an X-Windows compatible environment and a C++ compiler
  such as Gnu G++ and AT&T CC.  WireC is available via ftp on the Internet.
  For details send mail to

  [e-mail] [e-mail]

45: LateX circuit symbols for schematic generation

  (From Adrian Johnstone <[e-mail]>)

  A set of circuit schematic symbols are available for use in LaTeX picture
  mode. The set includes all basic logic gates in four orientations, FETs,
  power supply pins, transmission gates, capacitors, resistors and wiring
  T-junctions. All pins are on a 1mm grid and the symbols are designed to
  be easily used with Georg Horn's TeXcad program: we even supply you with